1. Field of the Invention
The present invention relates to high density memory technologies, including technologies that include three-dimensional 3D arrays of memory cells.
2. Description of Related Art
High density flash memory is used for nonvolatile storage in many systems. One popular architecture is known as NAND flash, and is usually implemented in a two-dimensional array of memory cells. As the manufacturing technology advances to smaller and smaller nodes, it is widely believed that two-dimensional NAND flash is reaching physical limitations. Thus, a wide variety of other technologies is being explored.
In one trend to achieve high density memory for flash memory and other types of memory, designers have been looking to techniques for stacking multiple levels of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006. See also, U.S. Pat. No. 8,482,052, by Lue et al., entitled “Silicon on Insulator and Thin Film Transistor Bandgap Engineered Split Gate Memory.”
In a second approach, flash memory has been implemented using vertical gate structures that are shared among many levels or memory cells. One 3D Vertical Gate (3DVG) architecture is described in U.S. Pat. No. 8,503,213 issued 6 Aug. 2013 (filed 1 Apr. 2011), entitled “Memory Architecture Of 3D Array With Alternating Memory String Orientation And String Select Structures,” by inventors Shih-Hung Chen and Hang-Ting Lue, which is incorporated by reference as if fully set forth herein.
In a third approach, flash memory has been implemented using vertical channel structures that are shared among many levels of memory cells. See for example, commonly owned U.S. Pat. No. 8,363,476, issued 29 Jan. 2013 (filed 19 Jan. 2011), entitled “Memory Device, Manufacturing Method And Operating Method Of The Same,” by inventors Hang-Ting Lue and Shi-Hung Chen. See, also, U.S. patent application Ser. No. 13/772,058, entitled “3D NAND Flash Memory,” filed 20 Feb. 2013, by inventor Hang-Ting Lue, which is incorporated by reference as if fully set forth herein.
Another structure that provides vertical channel structures for NAND cells in a charge trapping memory technology is described in Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007, pages: 14-15.
All of these 3D technologies have practical limits on the number of layers of memory cells that can be implemented, while maintaining reliable operation. The simple stacking approach is costly because each layer of the stack must be separately patterned. The vertical gate and vertical channel structures, or other structures that include vertical conductors that extend through multiple layers of memory cells, may be more cost effective, because many layers can be patterned using one mask and etch process. However, limitations arise because high aspect ratio structures are hard to etch, intermediate structures may break during processing, and so on.
It is desirable therefore to provide technologies that support stacking 3D blocks of memory cells to overcome some of the limitations in the number of layers that can be reliably achieved.